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74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state

Rev. 03 — 20 May 2008
Product data sheet
General description
The 74AHC373; 74AHCT373 is a high-speed Si-gate CMOS device and is pin compatiblewith Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standardNo. 7-A.
The 74AHC373; 74AHCT373 consists of eight D-type transparent latches featuringseparate D-type inputs for each latch and 3-state true outputs for bus orientedapplications. A latch enable input (LE) and an output enable input (OE) are common to alllatches.
When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition thelatches are transparent, i.e. a latch output will change state each time its correspondingDn input changes. When pin LE is LOW, the latches store the information that is presentat the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE.
When pin OE is LOW, the contents of the 8 latches are available at the outputs. Whenpin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OEinput does not affect the state of the latches.
The 74AHC373; 74AHCT373 is functionally identical to the 74AHC573; 74AHCT573, buthas a different pin arrangement.
Features
■ Balanced propagation delays■ All inputs have a Schmitt-trigger action■ Common 3-state output enable input■ Inputs accepts voltages higher than VCC■ Functionally identical to the 74AHC573; 74AHCT573■ Input levels: ◆ For 74AHC373: CMOS input level◆ For 74AHCT373: TTL input level ◆ HBM EIA/JESD22-A114E exceeds 2000 V◆ MM EIA/JESD22-A115-A exceeds 200 V◆ CDM EIA/JESD22-C101C exceeds 1000 V ■ Multiple package options■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Ordering information
Ordering information
Type number
Temperature range
Description
74AHC373
plastic thin shrink small outline package; 20 leads; 74AHCT373
plastic thin shrink small outline package; 20 leads; Functional diagram
Functional diagram
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Logic symbol
IEC logic symbol
Logic diagram
Logic diagram (one latch)
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Pinning information
5.1 Pinning
74AHC373
74AHCT373
Pin configuration SO20 and TSSOP20
5.2 Pin description
Pin description
Description
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Pin description …continued
Description
Functional description
Function table
Operating mode
Internal
Enable and read register (transparent mode) h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Limiting values
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Parameter
Conditions
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K.
For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K.
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Recommended operating conditions
Operating conditions
Parameter
Conditions
74AHC373
74AHCT373
Static characteristics
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 °C to +85 °C 40 °C to +125 °C Unit
74AHC373
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 °C to +85 °C 40 °C to +125 °C Unit
74AHCT373
pin; other inputs at VCC orGND; IO = 0 A; VCC = 5.5 V VI = VCC − 2.1 V; other pins atVCC or GND; IO = 0 A;VCC = 4.5 V to 5.5 V NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
10. Dynamic characteristics
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter
Conditions
40 °C to +85 °C 40 °C to +125 °C Unit
74AHC373
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter
Conditions
40 °C to +85 °C 40 °C to +125 °C Unit
Min Typ[1]
74AHCT373; VCC = 4.5 V to 5.5 V
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
CPD is used to determine the dynamic power dissipation (PD in µW).
P fi = input frequency in MHz;fo = output frequency in MHz;CL = output load capacitance in pF;VCC = supply voltage in V;N = number of inputs switching;Σ(C NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
11. Waveforms
VOL and VOH are typical voltage output levels that occur with the output load.
Data input to output propagation delays
VOL and VOH are typical voltage output levels that occur with the output load.
Latch enable pulse width and input to output propagation delays
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
VOL and VOH are typical voltage output levels that occur with the output load.
Enable and disable times
VOL and VOH are typical voltage output levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predicable output performance.
Fig 10. Data set-up and hold times
Measurement points
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
RT = termination resistance should be equal to output impedance Zo of the pulse generator.
CL = load capacitance including jig and probe capacitance.
Fig 11. Test circuitry for switching times
Test data
S1 position
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES
EUROPEAN
ISSUE DATE
PROJECTION
Fig 12. Package outline SOT163-1 (SO20)
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
DIMENSIONS (mm are the original dimensions)
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
EUROPEAN
ISSUE DATE
PROJECTION
Fig 13. Package outline SOT360-1 (TSSOP20)
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
13. Abbreviations
Table 10.
Abbreviations
Description
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
The format of this data sheet has been redesigned to comply with the new identity guidelines of
Legal texts have been adapted to the new company name where appropriate.
or the input leakage current have been changed.
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
15. Legal information
Data sheet status
Document status[1][2]
Product status[3]
Definition
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product statusinformation is available on the Internet at URL Definitions
malfunction of an NXP Semiconductors product can reasonably be expectedto result in personal injury, death or severe property or environmentaldamage. NXP Semiconductors accepts no liability for inclusion and/or use of Draft — The document is a draft version only. The content is still under
NXP Semiconductors products in such equipment or applications and internal review and subject to formal approval, which may result in therefore such inclusion and/or use is at the customer’s own risk.
modifications or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness of Applications — Applications that are described herein for any of these
information included herein and shall have no liability for the consequences of products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for thespecified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
Limiting values — Stress above one or more limiting values (as defined in
for quick reference only and should not be relied upon to contain detailed and the Absolute Maximum Ratings System of IEC 60134) may cause permanent full information. For detailed and full information see the relevant full data damage to the device. Limiting values are stress ratings only and operation of sheet, which is available on request via the local NXP Semiconductors sales the device at these or any other conditions above those given in the office. In case of any inconsistency or conflict with the short data sheet, the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
Disclaimers
subject to the general terms and conditions of commercial sale, as publishedat , including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unless General — Information in this document is believed to be accurate and
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of reliable. However, NXP Semiconductors does not give any representations or any inconsistency or conflict between information in this document and such warranties, expressed or implied, as to the accuracy or completeness of such terms and conditions, the latter will prevail.
information and shall have no liability for the consequences of use of such No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the Right to make changes — NXP Semiconductors reserves the right to make
grant, conveyance or implication of any license under any copyrights, patents changes to information published in this document, including without or other industrial or intellectual property rights.
limitation specifications and product descriptions, at any time and withoutnotice. This document supersedes and replaces all information supplied priorto the publication hereof.
Trademarks
Suitability for use — NXP Semiconductors products are not designed,
Notice: All referenced brands, product names, service names and trademarks authorized or warranted to be suitable for use in medical, military, aircraft, are the property of their respective owners.
space or life support equipment, nor in applications where failure or 16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 20 May 2008
NXP Semiconductors
74AHC373; 74AHCT373
Octal D-type transparant latch; 3-state
17. Contents
Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.
NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 May 2008
Document identifier: 74AHC_AHCT373_3

Source: http://www.knowing-tech.com.tw/data/74AHCT373.pdf

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